A cache memory is a relatively small, high speed memory that is used to increase the speed of a data processing system. The access time of the cache memory is close to the central processing unit (CPU) logic propagation delay. The cache memory stores frequently used instructions or data to reduce the number of accesses between the CPU and a relatively slower main memory, thus improving system performance.
A cache TAG is a necessary part of the cache memory. The cache TAG receives an address that is provided by the processor and determines if the requested instructions or data are present in the cache memory. Like the cache memory, the cache TAG has an array of conventional static random access memory (SRAM) cells. When data is written into the cache memory, the higher order bits of the address of the data are stored in the cache TAG. When in a read/compare mode, a comparator in the cache TAG compares a processor generated address to the TAG address. If the TAG address and the processor generated address are the same, a cache "hit" occurs, and a match signal of a predetermined logic state is provided by the cache TAG, indicating that the requested data is located in the cache memory. If the processor generated address and the TAG address are not the same, a cache "miss" occurs, and a match signal of an opposite logic state is provided by the cache TAG, indicating to the processor that the requested data is not located in the cache memory.
It is important for the match signal to be generated as quickly as possible after the cache TAG receives the data to be compared. In some prior art cache TAGs, the read data and the match signal share the same data path, which results in increased gate delay before the match signal can be provided to the processor. Also, the processor generated address and the TAG address may be at different logic levels, requiring either the processor generated address or the TAG address to first be level converted before a comparison can be accomplished, resulting in increased gate delay when generating the match signal. In addition, in the case of a hit, prior art cache TAGs that share a common data path cannot provide read data for the cache TAG at the same time that a match signal is provided.